Marvell's memory-interconnect opportunity now includes sharing more memory across inference hosts. Its second-generation Structera X CXL 3.2 controllers can support up to four hosts, with up to 6TB of DDR5 per controller and workload-dependent compression offering 2-3x effective capacity for longer contexts and KV caches, per Marvell. First-generation products ship to hyperscalers; the new controllers are expected to sample in Q1 2027, so customer adoption and production remain checkpoints. x.com