Finn Stockinger
Equity Analyst & Investor, Technology Research
TSMC's shift to CoWoS-L packaging creates quiet winners in Camtek, Onto Innovation and Disco, which address its new yield problems. Advanced packaging is AI's main bottleneck. CoWoS-L replaces rigid silicon interposers with organic substrates and tiny silicon bridges, which warp under heat and break microscopic solder joints. Camtek and Onto supply essential 3D inspection and metrology for those substrates, and Disco is a near-monopolist in dicing and grinding the bridges. x.comÂ
Nvidia's reported shift of Feynman chips to a hybrid of TSMC A16 and 3nm dies, forced by A16 capacity limits, favors companies enabling chiplet connectivity, yield and stacking. TSMC's SoIC and CoWoS fuse the dies with Applied Materials, Besi and Kulicke & Soffa tools. Broadcom, Marvell and POET lead optical links; Onto, Nova, Aehr and FormFactor handle inspection and test; Samsung, SK Hynix and Micron supply HBM4. Top picks: POET, Aehr, Onto, Applied Materials, Broadcom, Marvell and Samsung. x.comÂ
Growing chip-design complexity gives Onto Innovation's customers reason to keep investing beyond the current packaging recovery; Camtek offers more focused advanced-packaging exposure, with a technical edge in selected HBM applications. Onto is more closely tied to SK hynix's capital spending and also sells chip-fabrication metrology and packaging lithography. Industry information identifies Camtek as a preferred supplier for Samsung's HBM lines as Samsung invests to catch up. x.comÂ
TSMC may lose pricing power as performance gains shift from shrinking transistors to stacking, interconnects and optics, while logic folding could make older processes competitive. Despite strong leading-edge demand, investors may overestimate the profit share its node leadership can retain. Its cautious expansion and past reluctance toward advanced packaging suggest a risk-averse culture that protects returns but could leave it late to disruptive technologies and key customers. x.comÂ
Leading-edge wafer demand is bullish for semiconductor equipment makers because TSMC is already at over 100% utilization on those nodes. Per Ben Bajarin, rack-scale pods drive more wafers across categories. Close collaboration at the leading edge also gives equipment makers and TSMC visibility into plans years ahead. x.com x.comÂ
TSMC's conservative delay in high-NA adoption will be its downfall as Intel's stitching advances sooner. TSMC's larger-mask alternative requires changing the entire stage and is projected for production by 2033; Intel's stitching is substantially derisked and could be ready for volume production in 2027 at the earliest. TSMC's CoWoS and CoPoS shortcomings add to the concern. x.comÂ
Putting CPO optical engines in the interposer should make TSMC the leader at that packaging task. The OCI-MSA diagram shows an optical engine mounted on a high-density interposer; GlobalFoundries has a modest agreement in the area, but should not be expected to earn the same profit. x.comÂ
TSMC should benefit as CoWoS packaging is relieved, because the extra volume flows back into its front-end fabs. Per TrendForce, TSMC is taking CoWoS from about 130k wafers a month at end-2026 to 260k by end-2028, while 2nm and 3nm also grow. C.C. Wei said outside packaging capacity helps the wafer business, still most of TSMC. OSATs can win packaging while TSMC owns the bigger upstream prize. The view fails if CoWoS alternatives ramp and TSMC's HPC wafer growth stalls. x.comÂ
Chip-equipment makers look cheap given supply-chain shortages and demand visible toward 2029-30. At Semicon West, no one raised demand concerns; suppliers' suppliers lacked capacity, while several high-quality names trade below the S&P multiple. Per Lynx's KC, customers are asking about delivery three to four years out. For Lam Research's report, bottlenecks, pricing and visibility beyond 2027 matter more than demand. x.com x.comÂ
Camtek's AI inspection orders are now turning into sales as customers expand chip production and need tools to catch defects. Preliminary Q3 revenue of $160m is roughly 20% above Q2, with $179m forecast for Q4. x.comÂ
TSMC sits at the end of the money trail as agentic AI reprices the chip supply chain, and Google's $40 billion Anthropic deal is the clearest proof. That deal is effectively a prepaid inference contract for 5GW of TPU capacity over five years, and every TPU flows through TSMC, where advanced-node demand runs about 3x supply. Agentic AI burns 10-100x more compute per session than a chatbot. CoWoS packaging is the tighter bottleneck, with prices rising 10-20% a year, double logic wafers. x.com … Show more
As custom AI chips become normal, the scarce asset may be the capacity to build them, since every design passes through the same packaging, substrate, PCB material and manufacturing bottlenecks. Meta with MediaTek and Amazon with Alchip show chip design going modular. That favors TSMC for manufacturing, Alchip for ASIC back-end work, Samsung Electro-Mechanics, Ibiden and AT&S for high-end substrates, and Shengyi Technology if AI PCB material stays tight. The bottleneck map widened. x.com x.comÂ
