ASE's panel-level packaging implementation for AMD's Venice CPU gives both companies a reason to do great in the coming years. Per SemiAnalysis, ASE and its subsidiary SPIL implemented second-generation fan-out embedded bridge technology for Venice, with limited initial production targeted for Q1 2027. A 310 mm panel fits 25 interposers versus 22 on a 300 mm wafer, a modest 14% gain rather than a dramatic cost reduction. x.com















